Method for forming an insulator having a low dielectric constant on a semiconductor substrate

Abstract

A method for fabricating an insulator on a semiconductor substrate such that the insulator has a low dielectric constant. A first interconnect and a second interconnect are configured on a semiconductor substrate. A conductive silicon is formed between the first interconnect and the second interconnect. The conductive silicon is anodically etched in a hydrofluoric-acid-containing electrolyte to convert the conductive silicon into porous silicon. The porous silicon is subsequently oxidized to form porous silicon oxide. With a dielectric constant of between 1.1 and 4, the porous silicon oxide has a lower dielectric constant than customary silicon oxide with 4.

Claims

I claim: 1 . A method for fabricating an insulator on a semiconductor substrate, which comprises: providing a semiconductor substrate having a first interconnect and a second interconnect; forming amorphous silicon between the first interconnect and the second interconnect; anodically etching the amorphous silicon in a hydrofluoric-acid-containing electrolyte to convert the amorphous silicon into a porous silicon; and oxidizing the porous silicon to convert the porous silicon into a porous silicon oxide. 2 . The method according to claim 1 , which comprises performing the step of forming the amorphous silicon such that the amorphous silicon is conductive. 3 . The method according to claim 2 , which comprises performing the step of forming the amorphous silicon by depositing the porous silicon on the semiconductor substrate using a method selected from the group consisting of an LPCVD method, an PECVD method, and an RTCVD method. 4 . The method according to claim 1 , which comprises performing the step of forming the amorphous silicon by depositing the porous silicon on the semiconductor substrate using a method selected from the group consisting of an LPCVD method, an PECVD method, and an RTCVD method. 5 . The method according to claim 1 , which comprises performing the step of oxidizing the porous silicon with oxygen using a process selected from the group consisting of an RTP step, a furnace step, a plasma treatment, and anodic oxidation.
BACKGROUND OF THE INVENTION [0001] Field of the Invention [0002] The present invention relates to a method for fabricating an insulator having a low dielectric constant in which the insulator is located between interconnects on a semiconductor substrate. [0003] Electronic circuits that are connected to one another with electrical wiring are usually configured in semiconductor substrates. To that end, the electrical wiring is insulated from the semiconductor substrate by an insulating layer and the electronic components in the semiconductor substrate are connected to the metal wiring by so-called vias (contact holes). Since the electrical wiring has a row of interconnects which are formed relatively close together on the insulating layer, there is capacitive coupling between adjacent interconnects. The capacitive coupling between adjacent interconnects becomes greater, as the dielectric constant of the material located between the interconnects becomes higher. In this case, a large coupling capacitance has the disadvantage that electrical signals on the interconnects are delayed and attenuated by the high capacitance. [0004] Undoped or doped silicon oxide, silicon nitride or silicon oxynitride layers are usually used as dielectric layers between interconnects on a semiconductor chip. These layers have dielectric constants of between 4 and 7. The increasing miniaturization of the structures has the effect that the distance between two interconnects keeps on decreasing. As a result, the coupling capacitance between adjacent interconnects keeps on increasing. In this case, the extent of capacitive coupling is directly proportional to the dielectric constant of the insulating material configured between two interconnects. Known insulators having a dielectric constant of less than 4 are e.g. fluorine-doped oxides and organic materials. However, these materials have integration problems during interaction with customary semiconductor fabrication processes such as RIE (reactive ion etching), CMP (chemical mechanical polishing) and thermal processes, since organic materials are, for example, too unstable for these fabrication methods. SUMMARY OF THE INVENTION [0005] It is accordingly an object of the invention to provide a method for fabricating an insulator, between interconnects on a semiconductor substrate, which overcomes the above-mentioned disadvantageous of the prior art methods of this general type. In particular, it is an object of the invention to provide such a method to fabricate the insulator with a relatively low dielectric constant. [0006] With the foregoing and other objects in view there is provided, in accordance with the invention a method for fabricating an insulator on a semiconductor substrate. The method includes steps of: providing a semiconductor substrate having a first interconnect and a second interconnect; forming amorphous silicon between the first interconnect and the second interconnect; anodically etching the amorphous silicon in a hydrofluoric-acid-containing electrolyte to convert the amorphous silicon into a porous silicon; and oxidizing the porous silicon to convert the porous silicon into a porous silicon oxide. [0007] The advantage of the method is that well-known materials exhibiting good compatibility, such as silicon and silicon oxide, are used during the fabrication of the dielectric. A silicon oxide usually has a dielectric constant of 4 , which can be reduced to values of between 1.1 and 4 through the formation of a porous silicon oxide. In this case, silicon oxide and porous silicon oxide are compatible with process steps such as RIE, CMP and thermal processes. Therefore, porous silicon oxide is outstandingly suitable for forming an intermetal dielectric. [0008] By way of example, the formation of porous silicon is shown in “Spatial and quantum confinement in crystalline and amorphous porous silicon”, I. Solomon et al., Journal of Non-Crystalline Solids 227-230 (1998) 248-253, U.S. Pat. No. 5, 935,410, and “Study of Photoluminescence in Porous Silicon Prepared by Electrochemical Etching of Amorphous silicon”, E. Bhattacharya et al., Physics of Semiconductor Devices, 603-606 (1998). [0009] In accordance with an added feature of the invention, the conductive silicon is an amorphous silicon, a microcrystalline silicon, or a polysilicon. The aforementioned silicon structures are suitable for being converted into a porous silicon using a hydrofluoric-acid-containing electrolyte in an anodic etching process. In this case, porous silicon, involving a nanostructured material, is produced within a specific process regime. In this case, the degree of porosity can be varied between 20 and 90% by way of the process parameters. In this case, the porous silicon has a distinctly lower conductivity than the compact silicon from which it is formed. [0010] In accordance with an additional feature of the invention, the conductive silicon is deposited on the substrate by an LPCVD (low pressure chemical vapor deposition) method, a PECVD (plasma enchanced chemical vapor deposition) method, or an RTCVD (rapid thermal chemical vapor deposition) method. The advantage of the aforementioned deposition methods is that the conductive silicon is deposited conformally on interconnects configured on the substrate surface. Furthermore, the aforementioned methods are suitable for filling interspaces between interconnects in a manner free from shrink holes. This has the advantage that fewer gas inclusions are formed in the dielectric layer. [0011] In accordance with a concomitant feature of the invention, the oxidation of the porous silicon is carried out using an RTP (rapid thermal process) step, a furnace step, a plasma treatment or an anodic oxidation with the aid of oxygen. The aforementioned oxidation methods are advantageously suitable for forming a porous silicon oxide from the porous silicon. [0012] Other features which are considered as characteristic for the invention are set forth in the appended claims. [0013] Although the invention is illustrated and described herein as embodied in a method for forming an insulator having a low dielectric constant on a semiconductor substrate, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. [0014] The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0015] [0015]FIG. 1 shows a substrate with interconnects and a conductive silicon; [0016] [0016]FIG. 2 shows the substrate with the interconnects shown in FIG. 1, in which the conductive silicon has been converted into a porous silicon and then into a porous silicon oxide. DESCRIPTION OF THE PREFERRED EMBODIMENTS [0017] Referring now to the figures of the drawing in detail and first, particularly, to FIG. 1 thereof, there is shown a substrate 1 on which a first interconnect 2 and a second interconnect 3 are configured. Using a suitable deposition method, such as, for example, an LPCVD, PECVD, or RTCVD method, conductive silicon 4 is configured on the substrate 1 , the first interconnect 2 , and the second interconnect 3 , and between the first interconnect 2 and the second interconnect 3 . In this case, the conductive silicon may be formed for example as amorphous silicon, polysilicon or microcrystalline silicon. By way of example, an amorphous silicon can be converted into a microcrystalline or polycrystalline silicon by means of a thermal step. [0018] With reference to FIG. 2, an anodic etching step is carried out using a hydrofluoric-acid-containing electrolyte, the conductive silicon 4 being converted into porous silicon 5 . In a subsequent oxidation step, the porous silicon 5 is converted into a porous silicon oxide 6 . By way of example, an RTP step, a furnace step, a plasma treatment or an anodic oxidation is suitable for the oxidation. By way of example, electrolytes which do not contain hydrofluoric acid are suitable for the anodic oxidation. [0019] The oxidation is advantageously carried out using oxygen. [0020] What is advantageous about using an amorphous silicon layer 4 is the conformity of a deposited amorphous silicon layer 4 and the structure of the porous layer which is formed therefrom by means of anodic oxidation and which is converted, by oxidation, into a particularly advantageous insulator having a low dielectric constant. Advantage is attached to the uniformity and stable structure of the porous amorphous layer, whose number of pores can be made significantly larger than that of other deposited silicon layers and whose pore diameter can be made smaller, thereby enabling a higher integration density with smaller spacings between adjacent interconnects.

Description

Topics

Download Full PDF Version (Non-Commercial Use)

Patent Citations (0)

    Publication numberPublication dateAssigneeTitle

NO-Patent Citations (0)

    Title

Cited By (96)

    Publication numberPublication dateAssigneeTitle
    US-7387939-B2June 17, 2008Micron Technology, Inc.Methods of forming semiconductor structures and capacitor devices
    US-8350209-B2January 08, 2013X-Fab Semiconductor Foundries AgProduction of self-organized pin-type nanostructures, and the rather extensive applications thereof
    US-2008206950-A1August 28, 2008Micron Technology, Inc.Methods of forming a plurality of capacitors
    US-2010117196-A1May 13, 2010Manning Homer MSupport For Vertically-Oriented Capacitors During The Formation of a Semiconductor Device
    US-2007093022-A1April 26, 2007Cem Basceri, Sandhu Gurtej SIntegrated circuitry
    US-2011124168-A1May 26, 2011Micron Technology, Inc.Methods of Forming Field Effect Transistors, Methods of Forming Field Effect Transistor Gates, Methods of Forming Integrated Circuitry Comprising a Transistor Gate Array and Circuitry Peripheral to the Gate Array, and Methods of Forming Integrated Circuitry Comprising a Transistor Gate Array Including First Gates and Second Grounded Isolation Gates
    US-2010009512-A1January 14, 2010Fred FishburnMethods of forming a plurality of capacitors
    US-2011086476-A1April 14, 2011Micron Technology, Inc.Methods of Forming Field Effect Transistors on Substrates
    US-2010311219-A1December 09, 2010Micron Technology, Inc.Methods of Forming a Plurality of Capacitors
    US-9076757-B2July 07, 2015Micron Technology, Inc.Methods of forming a plurality of capacitors
    US-8389363-B2March 05, 2013Micron Technology, Inc.Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates
    US-8394699-B2March 12, 2013Micron Technology, Inc.Memory arrays and methods of fabricating memory arrays
    US-7785962-B2August 31, 2010Micron Technology, Inc.Methods of forming a plurality of capacitors
    US-8786001-B2July 22, 2014Round Rock Research, LlcSemiconductor devices
    US-7439152-B2October 21, 2008Micron Technology, Inc.Methods of forming a plurality of capacitors
    US-9595387-B2March 14, 2017Micron Technology, Inc.High aspect ratio openings
    US-7413952-B2August 19, 2008Micron Technology, Inc.Methods of forming a plurality of circuit components and methods of forming a plurality of structures suspended elevationally above a substrate
    US-8263457-B2September 11, 2012Micron Technology, Inc.Methods of forming a plurality of capacitors
    US-8164132-B2April 24, 2012Round Rock Research, LlcMethods of forming integrated circuit devices
    US-7445991-B2November 04, 2008Micron Technology, Inc.Methods of forming a plurality of capacitors
    US-8207563-B2June 26, 2012Round Rock Research, LlcIntegrated circuitry
    US-2008012070-A1January 17, 2008Werner JuenglingApparatus for a self-aligned recessed access device (rad) transistor gate
    US-8877589-B2November 04, 2014Micron Technology, Inc.Methods of forming field effect transistors on substrates
    US-2010261331-A1October 14, 2010Manning H MontgomeryMethods Of Forming A Plurality Of Capacitors
    US-9196673-B2November 24, 2015Micron Technology, Inc.Methods of forming capacitors
    US-2011186964-A1August 04, 2011Round Rock Research, LlcMethods of forming integrated circuit devices
    US-2006063345-A1March 23, 2006Manning H M, Graettinger Thomas M, Marsela PontohMethods of forming plurality of capacitor devices
    US-9076680-B2July 07, 2015Micron Technology, Inc.Integrated circuitry, methods of forming capacitors, and methods of forming integrated circuitry comprising an array of capacitors and circuitry peripheral to the array
    US-8129240-B2March 06, 2012Micron Technology, Inc.Methods of forming a plurality of capacitors
    US-8446762-B2May 21, 2013Micron Technology, Inc.Methods of making a semiconductor memory device
    US-7420238-B2September 02, 2008Micron Technology, Inc.Semiconductor constructions
    US-2005074918-A1April 07, 2005Taiwan Semicondutor Manufacturing Co.Pad structure for stress relief
    US-8518788-B2August 27, 2013Micron Technology, Inc.Methods of forming a plurality of capacitors
    US-2007196978-A1August 23, 2007Manning H MIntegrated circuitry comprising a pair of adjacent capacitors
    US-9536971-B2January 03, 2017Micron Technology, Inc.Semiconductor device comprising a transistor gate having multiple vertically oriented sidewalls
    US-8399920-B2March 19, 2013Werner JuenglingSemiconductor device comprising a transistor gate having multiple vertically oriented sidewalls
    US-2006211211-A1September 21, 2006Sandhu Gurtej S, Durcan D MMethods of forming pluralities of capacitors
    US-7825451-B2November 02, 2010Micron Technology, Inc.Array of capacitors with electrically insulative rings
    US-2006246678-A1November 02, 2006Manning H MMethods of forming a plurality of capacitors
    US-7557013-B2July 07, 2009Micron Technology, Inc.Methods of forming a plurality of capacitors
    US-2005287780-A1December 29, 2005Micron Technology, Inc.Semiconductor constructions
    US-7544563-B2June 09, 2009Micron Technology, Inc.Methods of forming a plurality of capacitors
    US-8916912-B2December 23, 2014Micron Technology, Inc.Semiconductor device comprising a transistor gate having multiple vertically oriented sidewalls
    US-2010151653-A1June 17, 2010Micron Technology, Inc.Methods Of Forming A Plurality Of Capacitors
    US-2008090416-A1April 17, 2008Micro Technology, Inc.Methods of etching polysilicon and methods of forming pluralities of capacitors
    US-2007161202-A1July 12, 2007Manning H MMethods of forming a plurality of capacitors
    US-8946043-B2February 03, 2015Micron Technology, Inc.Methods of forming capacitors
    US-8450164-B2May 28, 2013Micron Technology, Inc.Methods of forming a plurality of capacitors
    US-8551823-B2October 08, 2013Micron Technology, Inc.Methods of forming lines of capacitorless one transistor DRAM cells, methods of patterning substrates, and methods of forming two conductive lines
    US-2009209080-A1August 20, 2009Sandhu Gurtej S, Durcan D MarkMethods of Forming Pluralities of Capacitors
    US-8163613-B2April 24, 2012Micron Technology, Inc.Methods of forming a plurality of capacitors
    US-7972954-B2July 05, 2011Infineon Technologies AgPorous silicon dielectric
    US-2011127641-A1June 02, 2011X-Fab Semiconductor Foundries Ag, Technische Universitaet IImenauSelf-organized pin-type nanostructures, and production thereof on silicon
    US-7445990-B2November 04, 2008Micron Technology, Inc.Methods of forming a plurality of capacitors
    US-7557015-B2July 07, 2009Micron Technology, Inc.Methods of forming pluralities of capacitors
    US-2009261353-A1October 22, 2009X-Fab Semiconductor Foundries AgProduction of self-organized pin-type nanostructures, and the rather extensive applications thereof
    US-7393743-B2July 01, 2008Micron Technology, Inc.Methods of forming a plurality of capacitors
    US-2006261440-A1November 23, 2006Micron Technology, Inc.Methods of forming a plurality of capacitors, and integrated circuitry comprising a pair of capacitors
    US-9129847-B2September 08, 2015Micron Technology, Inc.Transistor structures and integrated circuitry comprising an array of transistor structures
    US-9224798-B2December 29, 2015Micron Technology, Inc.Capacitor forming methods
    US-2007238259-A1October 11, 2007Micron Technology, Inc.Methods of forming a plurality of capacitors
    US-2006148190-A1July 06, 2006Busch Brett W, Fishburn Fred D, James RomingerMethods of forming a plurality of capacitors
    DE-112007000215-B4January 22, 2015Infineon Technologies AgVerfahren zur Herstellen einer Halbleitervorrichtung mit porösem Silizium-Dielektrikum
    US-2009176011-A1July 09, 2009Mark KiehlbauchCapacitor Forming Methods
    US-7534694-B2May 19, 2009Micron Technology, Inc.Methods of forming a plurality of capacitors
    US-7585741-B2September 08, 2009Micron Technology, Inc.Methods of forming capacitors
    US-2009239343-A1September 24, 2009Fernando GonzalezMethods Of Forming Lines Of Capacitorless One Transistor DRAM Cells, Methods Of Patterning Substrates, And Methods Of Forming Two Conductive Lines
    US-2007134872-A1June 14, 2007Sandhu Gurtej S, Manning H M, Kramer Stephen JMethods of forming pluralities of capacitors
    US-8274777-B2September 25, 2012Micron Technology, Inc.High aspect ratio openings
    US-7682924-B2March 23, 2010Micron Technology, Inc.Methods of forming a plurality of capacitors
    US-7915136-B2March 29, 2011Round Rock Research, LlcMethods of forming integrated circuit devices
    US-8652926-B1February 18, 2014Micron Technology, Inc.Methods of forming capacitors
    US-8760841-B2June 24, 2014Micron Technology, Inc.High aspect ratio openings
    US-2006263968-A1November 23, 2006Micron Technology, Inc.Methods of forming pluralities of capacitors
    US-7919386-B2April 05, 2011Micron Technology, Inc.Methods of forming pluralities of capacitors
    US-2007173030-A1July 26, 2007Micron Technology, Inc.Methods of forming a plurality of capacitors
    US-2010266962-A1October 21, 2010Micron Technology, Inc.Methods Of Forming A Plurality Of Capacitors
    US-8388851-B2March 05, 2013Micron Technology, Inc.Capacitor forming methods
    US-7858486-B2December 28, 2010Micron Technology, Inc.Methods of forming a plurality of capacitors
    US-7271051-B2September 18, 2007Micron Technology, Inc.Methods of forming a plurality of capacitor devices
    US-2011012182-A1January 20, 2011Micron Technology Inc.Semiconductor Constructions and Transistors, and Methods of Forming Semiconductor Constructions and Transistors
    US-7517753-B2April 14, 2009Micron Technology, Inc.Methods of forming pluralities of capacitors
    US-8734656-B2May 27, 2014Micron Technology, Inc.Capacitor forming methods
    US-2007105303-A1May 10, 2007Busch Brett W, Fishburn Fred D, James RomingerMethods of forming a plurality of circuit components and methods of forming a plurality of structures suspended elevationally above a substrate
    US-8120101-B2February 21, 2012Micron Technology, Inc.Semiconductor constructions and transistors, and methods of forming semiconductor constructions and transistors
    US-7759193-B2July 20, 2010Micron Technology, Inc.Methods of forming a plurality of capacitors
    US-7902081-B2March 08, 2011Micron Technology, Inc.Methods of etching polysilicon and methods of forming pluralities of capacitors
    US-2006046420-A1March 02, 2006Manning H MMethods of forming a plurality of capacitors
    US-8426273-B2April 23, 2013Micron Technology, Inc.Methods of forming field effect transistors on substrates
    US-2006249798-A1November 09, 2006Manning H MMethods of forming capacitors
    US-2006014344-A1January 19, 2006Manning H MMethods of forming semiconductor structures and capacitor devices
    US-7449391-B2November 11, 2008Micron Technology, Inc.Methods of forming plurality of capacitor devices
    US-2007173073-A1July 26, 2007Frank WeberPorous silicon dielectric
    US-2009251845-A1October 08, 2009Micron Technology, Inc.High aspect ratio openings
    US-8058086-B2November 15, 2011X-Fab Semiconductor Foundries Ag, Technische Universitaet IlmenauSelf-organized pin-type nanostructures, and production thereof on silicon
    US-7393741-B2July 01, 2008Micron Technology, Inc.Methods of forming pluralities of capacitors