Methods of forming insulating materials, and methods of forming insulating materials around a conductive component

Abstract

In one aspect, the invention encompasses a method of forming an insulating material around a conductive component. A first material is chemical vapor deposited over and around a conductive component. Cavities are formed within the first material. After the cavities are formed, at least some of the first material is transformed into an insulative second material. In another aspect, the invention encompasses a method of forming an insulating material. Polysilicon is deposited proximate a substrate. A porosity of the polysilicon is increased. After the porosity is increased, at least some of the polysilicon is transformed into silicon dioxide.

Claims

What is claimed is: 1. A method of forming an insulating material comprising: depositing polysilicon proximate a substrate; forming cavities within the polysilicon to enhance porosity of the polysilicon; and after forming the cavities, transforming the polysilicon into porous silicon dioxide. 2. A method of forming an insulating material, comprising: forming polysilicon proximate a substrate; forming cavities within the polysilicon to enhance porosity of the polysilicon; after forming the cavities, transforming the polysilicon into porous silicon dioxide; and forming at least one structure over the porous silicon dioxide. 3. The method of claim 1 wherein the porous silicon dioxide comprises a volume, wherein the cavities comprise a cavity volume, and wherein the cavity volume is less than or equal to about 50% of the volume of the porous silicon dioxide. 4. The method of claim 2 wherein the formed polysilicon has a first volume before forming cavities, and wherein the forming cavities removes greater than about 50% of said first volume of the formed polysilicon. 5. The method of claim 2 wherein the forming polysilicon comprises chemical vapor deposition. 6. The method of claim 1 wherein the forming cavities comprises electrochemical anodization. 7. The method of claim 1 wherein the forming cavities comprises subjecting the polysilicon to a chemical etch. 8. The method of claim 1 wherein the forming cavities comprises: doping the polysilicon with a p-type dopant; and subjecting the doped polysilicon to a phosphoric acid etch. 9. The method of claim 1 wherein the porous silicon dioxide comprises a dielectric constant of less than 4. 10. The method of claim 1 wherein the porous silicon dioxide comprises a dielectric constant of less than or equal to about 1.6.
TECHNICAL FIELD The invention pertains to methods of forming insulating material, such as for example, methods of forming insulating material between components of integrated circuits. BACKGROUND OF THE INVENTION In methods of forming integrated circuits, it is frequently desired to isolate components of the integrated circuits from one another with insulative material. Such insulative material may comprise a number of materials, including, for example, silicon dioxide, silicon nitride, and undoped semiconductive material, such as silicon. Although such materials have acceptable insulative properties in many applications, the materials disadvantageously have high dielectric constants which can lead to capacitive coupling between proximate conductive elements. For instance, silicon dioxide has a dielectric constant of about 4, silicon nitride has a dielectric constant of about 8, and undoped silicon has a dielectric constant of about 12. It would be desirable to develop alternative methods for insulating conductive elements from one another with low-die lectric-constant materials. SUMMARY OF THE INVENTION The invention encompasses methods of forming insulating materials proximate conductive elements. In one aspect, the invention encompasses a method of forming an insulating material proximate a substrate in which a first material is chemical vapor deposited proximate the substrate. Cavities are formed within the first material, and, after forming the cavities, at least some of the first material is transformed into an insulative second material. In another aspect, the invention encompasses a method of forming an insulating material proximate a substrate in which porous polysilicon is formed proximate the substrate and at least some of the porous polysilicon is transformed into porous silicon dioxide. In yet another aspect, the invention encompasses a method of forming an insulating material between components of an integrated circuit. Polysilicon is chemical vapor deposited between two components and electrochemically anodized to convert the polysilicon into a porous mass having a first volume. The first volume comprises a polysilicon volume and a cavity volume, with the cavity volume comprising greater than or equal to about 75% of the first volume. The porous polysilicon mass is oxidized to transform the polysilicon into porous silicon dioxide having a second volume. The second volume comprises a silicon dioxide volume and a cavity volume, with the cavity volume comprising less than or equal to about 50% of said second volume. BRIEF DESCRIPTION OF THE DRAWINGS Preferred embodiments of the invention are described below with reference to the following accompanying drawings. FIG. 1 is a diagrammatic cross-sectional view of a semiconductor wafer fragment at a preliminary step of a processing method of the present invention. FIG. 2 is a view of the FIG. 1 wafer fragment shown at a processing step subsequent to that of FIG. 1 . FIG. 3 is a view of the FIG. 1 wafer fragment shown at a processing step subsequent to that of FIG. 2 . FIG. 4 is a view of the FIG. 1 wafer fragment shown at a processing step subsequent to that of FIG. 3 . FIG. 5 is a view of the FIG. 4 wafer fragment shown at a processing step subsequent to that of FIG. 4 . DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8). FIG. 1 shows a semiconductive wafer fragment 10 at a preliminary processing step of the present invention. Wafer fragment 10 comprises a substrate 12 and conductive elements 14 and 16 overlying substrate 12 . Substrate 12 may comprise, for example, a monocrystalline silicon wafer. To aid in interpretation of the claims that follow, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. Conductive elements 14 and 16 may comprise, for example, conductive lines. Conductive elements 14 and 16 might be part of an integrated circuit, for example. Although conductive elements 14 and 16 are illustrated as being horizontally displaced, such elements could also be displaced along a non-horizontal axis. For example, such elements could be vertically displaced from one another. An insulative material 18 is formed between substrate 12 and conductive elements 14 and 16 . Insulative material 18 can comprise a number of materials known to persons of ordinary skill in the art, such as, for example, silicon nitride and silicon dioxide. Insulative material 18 is provided to electrically isolate conductive elements 14 and 16 from substrate 12 . Such electrical isolation might be desired, for example, if substrate 12 is conductive or semiconduc:tive. Referring to FIG. 2, a first material 20 is deposited proximate substrate 12 and between conductive elements 14 and 16 . First material 20 preferably comprises polysilicon, and is preferably formed by chemical vapor depositing. Methods for chemical vapor depositing polysilicon are known to persons of ordinary skill in the art, and include, for example, methods comprising thermal decomposition of silane. Referring to FIG. 3, cavities 22 are formed within first material 20 . The formation of cavities 22 within first material 20 converts first material 20 into a porous first material. In a preferred example in which first material 20 comprises polysilicon, cavities 22 may be formed by, for example, either electrochemical anodization or by subjecting the polysilicon to a chemical etch. An example method of electrochemical anodization comprises doping preferred polysilicon layer 20 and making wafer fragment 10 an anode in an aqueous hydrofluoric acid solution. The hydrofluoric acid solution can comprise, for example, 20 wt. % HF, and the amount of current applied with wafer fragment 10 as anode can comprise, for example, about 10 mA for a 100 mm diameter wafer. An example method of chemical etching comprises doping preferred polysilicon layer 20 with a p-type conductivity-enhancing dopant and subsequently chemically etching layer 20 with a phosphoric acid solution. Preferably, greater than about 50% of a volume of layer 20 will be removed in forming cavities 22 . More preferably, at least about 75% of a volume of layer 20 will be removed in forming cavities 22 . In other words, the formation of cavities 22 converts the first material of layer 20 into a porous mass having a first volume which comprises a polysilicon volume and a cavity volume, wherein the cavity volume is most preferably greater than or equal to about 75% of the first volume. Referring to FIG. 4, first material 20 (shown in FIG. 3) is transformed into an insulative second material 30 . Where the first material 20 comprises polysilicon, such transformation can occur, for example, by oxidizing polysilicon layer 20 to transform such polysilicon layer to a silicon dioxide layer 30 . Methods for oxidizing a polysilicon layer are known to persons of ordinary skill in the art, and include, for example, thermal oxidation utilizing one or more of the oxygen-containing compounds O 2 , O 3 and H 2 O. In the shown embodiment, substantially all of first material 20 is transformed into insulative second material 30 . However, it is to be understood that the invention also encompasses embodiments in which only some of first material 20 is transformed into insulative second material 30 . In the shown preferred embodiment, oxidation of polysilicon layer 20 (shown in FIG. 3) having a first volume swells the layer into a silicon dioxide layer 30 having a second volume which is larger than the first volume. The increase in volume of layer 30 relative to layer 20 changes the relative volume occupied by cavities 22 . For instance, in an example embodiment in which cavities 22 comprise a cavity volume greater than or equal to about 75% of a first volume of porous polysilicon layer 20 (shown in FIG. 3 ), the cavity volume can comprise less than or equal to about 50% of a volume of porous silicon dioxide layer 30 formed by oxidizing such layer 20 . The cavities 22 within second material layer 30 lower a dielectric constant of the material relative to what the dielectric constant would be in the absence of cavities 22 . Cavities 22 will preferably be filled with some gas. Gases typically have a dielectric constant of about 1, which is less than a dielectric constant of most commonly used insulative materials. For instance, if the insulative solid material of layer 30 comprises silicon dioxide, the silicon dioxide will typically have a dielectric constant of about 4. The addition of cavities 22 within material layer 30 decreases the dielectric constant of the material 30 to less than 4. In the above-described embodiment in which cavities 22 comprise about 50% of the total volume of layer 30 , and in which layer 30 comprises silicon dioxide, layer 30 can have a dielectric constant of about 1.6. Accordingly, the method of the present invention can form a porous silicon dioxide insulative layer having a dielectric 1 constant of less than or equal to about 1.6. As shown in FIG. 5, layer 30 can be utilized to support additional circuitry formed over conductive elements 14 and 16 . In the shown embodiment, a filling layer 32 is provided over layer 30 . Filling layer 32 can comprises any of a number of materials known to persons of ordinary skill in the art, including, for example, insulative materials such as silicon dioxide or silicon nitride. Filling layer 32 can be provided by, for example, chemical vapor deposition. Filling layer 32 is planarized, such as, for example, by chemical-mechanical polishing, to form a substantially planar upper surface 34 . After forming a planar upper surface 34 over layer 30 , circuit elements 40 , 42 and 44 are formed over the upper surface. Circuit elements 40 , 42 and 44 can be formed by conventional methods. In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.

Description

Topics

Download Full PDF Version (Non-Commercial Use)

Patent Citations (36)

    Publication numberPublication dateAssigneeTitle
    US-3919060-ANovember 11, 1975IbmMethod of fabricating semiconductor device embodying dielectric isolation
    US-3954523-AMay 04, 1976International Business Machines CorporationProcess for fabricating devices having dielectric isolation utilizing anodic treatment and selective oxidation
    US-3979230-ASeptember 07, 1976General Electric CompanyMethod of making isolation grids in bodies of semiconductor material
    US-3998662-ADecember 21, 1976General Electric CompanyMigration of fine lines for bodies of semiconductor materials having a (100) planar orientation of a major surface
    US-4063901-ADecember 20, 1977Nippon Electric Company, Ltd.Method of manufacturing a semiconductor device
    US-4180416-ADecember 25, 1979International Business Machines CorporationThermal migration-porous silicon technique for forming deep dielectric isolation
    US-4561173-ADecember 31, 1985U.S. Philips CorporationMethod of manufacturing a wiring system
    US-5023200-AJune 11, 1991The United States Of America As Represented By The United States Department Of EnergyFormation of multiple levels of porous silicon for buried insulators and conductors in silicon device technologies
    US-5103288-AApril 07, 1992Nec CorporationSemiconductor device having multilayered wiring structure with a small parasitic capacitance
    US-5141896-AAugust 25, 1992Nec CorporationProcess for the production of crossing points for interconnections of semiconductor devices
    US-5171713-ADecember 15, 1992Micrunity Systems EngProcess for forming planarized, air-bridge interconnects on a semiconductor substrate
    US-5192834-AMarch 09, 1993Sumitomo Electric Industries, Ltd.Insulated electric wire
    US-5461003-AOctober 24, 1995Texas Instruments IncorporatedMultilevel interconnect structure with air gaps formed between metal leads
    US-5470801-ANovember 28, 1995Lsi Logic CorporationLow dielectric constant insulation layer for integrated circuit structure and method of making same
    US-5488015-AJanuary 30, 1996Texas Instruments IncorporatedMethod of making an interconnect structure with an integrated low density dielectric
    US-5496773-AMarch 05, 1996Micron Technology, Inc.Semiconductor processing method of providing an electrically conductive interconnecting plug between an elevationally inner electrically conductive node and an elevationally outer electrically conductive node
    US-5525857-AJune 11, 1996Texas Instruments Inc.Low density, high porosity material as gate dielectric for field emission device
    US-5527737-AJune 18, 1996Texas Instruments IncorporatedSelective formation of low-density, low-dielectric-constant insulators in narrow gaps for line-to-line capacitance reduction
    US-5554567-ASeptember 10, 1996Taiwan Semiconductor Manufacturing Company Ltd.Method for improving adhesion to a spin-on-glass
    US-5583078-ADecember 10, 1996Lucent Technologies Inc.Method for fabricating a planar dielectric
    US-5599745-AFebruary 04, 1997Micron Technology, Inc.Method to provide a void between adjacent conducting lines in a semiconductor device
    US-5629238-AMay 13, 1997Samsung Electronics Co., Ltd.Method for forming conductive line of semiconductor device
    US-5670828-ASeptember 23, 1997Advanced Micro Devices, Inc.Tunneling technology for reducing intra-conductive layer capacitance
    US-5691565-ANovember 25, 1997Micron Technology, Inc.Integrated circuitry having a pair of adjacent conductive lines
    US-5691573-ANovember 25, 1997Advanced Micro Devices, Inc.Composite insulation with a dielectric constant of less than 3 in a narrow space separating conductive lines
    US-5736425-AApril 07, 1998Texas Instruments IncorporatedGlycol-based method for forming a thin-film nanoporous dielectric
    US-5744399-AApril 28, 1998Lsi Logic CorporationProcess for forming low dielectric constant layers using fullerenes
    US-5773363-AJune 30, 1998Micron Technology, Inc.Semiconductor processing method of making electrical contact to a node
    US-5804508-ASeptember 08, 1998Texas Instruments IncorporatedMethod of making a low dielectric constant material for electronics
    US-5807607-ASeptember 15, 1998Texas Instruments IncorporatedPolyol-based method for forming thin film aerogels on semiconductor substrates
    US-5861345-AJanuary 19, 1999Chou; Chin-Hao, Yang; Yu-Chen, Hung; Shing-HsiangIn-situ pre-PECVD oxide deposition process for treating SOG
    US-5882978-AMarch 16, 1999Micron Technology, Inc.Methods of forming a silicon nitride film, a capacitor dielectric layer and a capacitor
    US-5883014-AMarch 16, 1999United Microelectronics Corp.Method for treating via sidewalls with hydrogen plasma
    US-5950102-ASeptember 07, 1999Industrial Technology Research InstituteMethod for fabricating air-insulated multilevel metal interconnections for integrated circuits
    US-6001747-ADecember 14, 1999Vlsi Technology, Inc.Process to improve adhesion of cap layers in integrated circuits
    US-6028015-AFebruary 22, 2000Lsi Logic CorporationProcess for treating damaged surfaces of low dielectric constant organo silicon oxide insulation material to inhibit moisture absorption

NO-Patent Citations (13)

    Title
    Abstract: Anderson, R.C. et. al., "Porous Polycrystalline Silicon: A New Material For MEMS", Jnl. of Microelectromechanical Systems (Mar. 1994), vol. 3, No. 1, pp. 10-18.
    Abstract: SiLK Polymer Coating With Low Dielectric Constant and High Thermal Stability for ULSI Interlayer Dielectric, P.H. Townsend et al., The Dow Chemical Company, Midland, MI, 9 pages (Undated).
    Anand, M.B., "Nura: A Feasible, Gas-Dielectric Interconnect Process", 1996 Sympos. on VLSI Technology Digest of Technical Papers, IEEE No month available 1996, PP. 82-83.
    Anderson, R.C. et al., "Porous polycrystalline silicon: A new material for MEMS", Journal of Microelectromechanical systems, vol. 3, No. 1, pp. 10-18, Mar. 1994.*
    Low Dielectric Constant Materials and Methods for Interlayer Dielectric Films in Ultralarge-Scale Integrated Circuit Multilevel Interconnections, Tetsuya Homma, Materials Science &Engr., R23, pp. 243-285 (1998).
    Product Brochure and Material Safety Data Sheet, Interlayer Dielectric, JSR Microelectronics, 12 pages (1997).
    Silicon Processing for the VLSI Era- vol. 1: Process Technology, Wolf, Ph.D., et al., Lattice Press (C)1986, pp. 429-437.
    Silicon Processing For The VLSI ERA, by Stanley Wolf Ph.D., (C)1986 Lattice Press pp. 1-8. No month available.
    Singer, Peter, "The New Low-k Candidate: It's a Gas", (Technology News/Wafer Processing) Semiconductor International, 1 Page, (Mar. 1989).
    The New IEEE Standard Dictionary of Electrical and Electronics Terms, (C)1993 IEEE, Inc., p. 662. Jan. 15, 1993.
    Togo, M., "A Gate-side Air-gap Structure (GAS) to Reduce the Parasitic Capacitance in MOSFETs", 1996 Sympos. on VLSI Technology Digest of Technical Papers, IEEE No month available 1996, pp. 38-39.
    U.S. application No. 08/947,847, Juengling et al., filed Oct. 9, 1997.
    Watanabe, H., "A Novel Stacked Capacitor with Porous-Si Electrodes for High Density DRAMs", Microelectronics Research Laboratories, NEC Corp., date unknown, pp. 17-18.

Cited By (43)

    Publication numberPublication dateAssigneeTitle
    US-2002115308-A1August 22, 2002Semiconductor Technology Academic Research CenterSemiconductor device with porous interlayer insulating film
    US-2002175405-A1November 28, 2002Micron Technology, Inc.Insulators for high density circuits
    US-2003068879-A1April 10, 2003Mcdaniel Terrence, Hineman Max F.Methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry
    US-2004061196-A1April 01, 2004Micron Technology, Inc.Methods for making nearly planar dielectric films in integrated circuits
    US-2004127036-A1July 01, 2004Micron Technology, Inc., A Corporation Of DelawareSemiconductor device with electrically coupled spiral inductors
    US-2004169453-A1September 02, 2004Ahn Kie Y., Leonard ForbesField emission display having reduced power requirements and method
    US-2004189175-A1September 30, 2004Ahn Kie Y., Leonard ForbesField emission display having reduced power requirements and method
    US-2005023695-A1February 03, 2005Micron Technology, Inc.Methods for making nearly planar dielectric films in integrated circuits
    US-2005026351-A1February 03, 2005Micron Technology, Inc.Packaging of electronic chips with air-bridge structures
    US-2005029663-A1February 10, 2005Micron Technology, Inc.Polynorbornene foam insulation for integrated circuits
    US-2005099260-A1May 12, 2005Micron Technology, Inc., A Corporation Of DelawareSemiconductor device with electrically coupled spiral inductors
    US-2005285220-A1December 29, 2005Micron Technology, Inc.Packaging of electronic chips with air-bridge structures
    US-2006001022-A1January 05, 2006Micron Technology, Inc.Methods for making nearly planar dielectric films in integrated circuits
    US-2006152134-A1July 13, 2006Micron Technology, Inc.Field emission display having reduced power requirements and method
    US-2006244112-A1November 02, 2006Micron Technology, Inc.Packaging of electronic chips with air-bridge structures
    US-2006246736-A1November 02, 2006Micron Technology, Inc.Methods for making nearly planar dielectric films in integrated circuits
    US-2006261435-A1November 23, 2006Micron Technology, Inc.Methods for making nearly planar dielectric films in integrated circuits
    US-2007042595-A1February 22, 2007Micron Technology, Inc.Packaging of electronic chips with air-bridge structures
    US-6333556-B1December 25, 2001Micron Technology, Inc.Insulating materials
    US-6350679-B1February 26, 2002Micron Technology, Inc.Methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry
    US-6352933-B1March 05, 2002Micron Technology, Inc.Methods of forming insulating materials between conductive components and methods of forming insulating materials around a conductive component
    US-6506678-B1January 14, 2003Lsi Logic CorporationIntegrated circuit structures having low k porous aluminum oxide dielectric material separating aluminum lines, and method of making same
    US-6548107-B2April 15, 2003Micron Technology, Inc.Methods of forming an insulating material proximate a substrate, and methods of forming an insulating material between components of an integrated circuit
    US-6635948-B2October 21, 2003Micron Technology, Inc.Semiconductor device with electrically coupled spiral inductors
    US-6710428-B2March 23, 2004Micron Technology, Inc.Porous silicon oxycarbide integrated circuit insulator
    US-6710538-B1March 23, 2004Micron Technology, Inc.Field emission display having reduced power requirements and method
    US-6713364-B2March 30, 2004Infineon Technologies AgMethod for forming an insulator having a low dielectric constant on a semiconductor substrate
    US-6794754-B2September 21, 2004Hiroshi Morisaki, Shinji NozakiSemiconductor device with porous interlayer insulating film
    US-6803326-B2October 12, 2004Micron Technology, Inc.Porous silicon oxycarbide integrated circuit insulator
    US-6812160-B2November 02, 2004Micron Technology, Inc.Methods of forming materials between conductive electrical components, and insulating materials
    US-6812163-B2November 02, 2004Semiconductor Technology Academic Research CenterSemiconductor device with porous interlayer insulating film
    US-6835111-B2December 28, 2004Micron Technology, Inc.Field emission display having porous silicon dioxide layer
    US-6844255-B2January 18, 2005Micron Technology, Inc.Methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry
    US-6953375-B2October 11, 2005Micron Technology, Inc.Manufacturing method of a field emission display having porous silicon dioxide insulating layer
    US-6979848-B2December 27, 2005Micron Technology, Inc.Memory system with conductive structures embedded in foamed insulator
    US-7023316-B2April 04, 2006Micron Technology, Inc.Semiconductor device with electrically coupled spiral inductors
    US-7030725-B2April 18, 2006Micron Technology, Inc.Semiconductor device with electrically coupled spiral inductors
    US-7042148-B2May 09, 2006Micron Technology, Inc.Field emission display having reduced power requirements and method
    US-7112542-B2September 26, 2006Micron Technology, Inc.Methods of forming materials between conductive electrical components, and insulating materials
    US-7125800-B2October 24, 2006Micron Technology, Inc.Methods for making nearly planar dielectric films in integrated circuits
    US-7235865-B2June 26, 2007Micron Technology, Inc.Methods for making nearly planar dielectric films in integrated circuits
    US-7262503-B2August 28, 2007Micron Technology, Inc.Semiconductor constructions
    US-7276788-B1October 02, 2007Micron Technology, Inc.Hydrophobic foamed insulators for high density circuits